1. Field of the invention
The present invention generally relates to an output circuit of a semiconductor memory device, and more particularly, the present invention relates to a circuit for setting to an output node voltage corresponding to a data output node from a memory cell.
This application is a counterpart of Japanese application Ser. No. 258196/1997, filed Sep. 24, 1997, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
A conventional related art is generally disclosed in Japanese Patent Laid Open No. 7-192468. A conventional output circuit is made up of a transistor for transferring a voltage of a power supply voltage node to an output node, a comparator which is activated in response to a timing clock signal and which compares a voltage of the power supply voltage node and a reference voltage, and another transistor which is connected between the power supply voltage node and a power supply voltage and which forms a current path between the power supply voltage node and the power supply voltage by turning on in response to an output signal of the comparator.
In the conventional output circuit, at first, the power supply voltage node set to a ground potential. The current path is formed between the power supply voltage node and the power supply voltage in response to a compared result of the comparator after a timing of the clock signal. The voltage of the power supply voltage node is rises as a result of the charge. As a result, a voltage rise rate of the power supply voltage node is slow.
In the conventional output circuit, it is desirable to increase an operation speed.